Engineers at Stanford, Carnegie Mellon, MIT, and the University of Pennsylvania have built a prototype chip that stacks memory and computing power vertically — like a high-rise instead of a sprawl — and early tests show it runs AI tasks in a fraction of the time current chips need.
The breakthrough tackles a problem that's plagued chip design for decades: the "memory wall." On today's flat chips, computing elements work far faster than data can reach them. It's like having a brilliant chef with only one narrow hallway to bring ingredients. The further data has to travel, the more the chip waits idle.
The new design flips that logic. By stacking memory and processing units vertically and connecting them with high-speed pathways, data moves in parallel — imagine dozens of elevators instead of a single staircase. In early hardware tests, the 3D prototype outperforms comparable 2D chips by roughly four times. Simulations of taller future versions, with more stacked layers, show even steeper gains: up to twelve-fold improvements on real AI workloads, including models derived from Meta's open-source LLaMA.
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The key is density and proximity. Each vertical layer brings memory closer to the computing units that need it, slashing the distance data has to travel. The design also opens a path to something chip engineers thought impossible: achieving both higher speed and lower energy consumption simultaneously. Current flat architectures force a trade-off — go faster, burn more power. The 3D approach could deliver 100- to 1,000-fold improvements in energy-delay product, a metric that balances throughput against power draw.
"The memory wall and the miniaturization wall form a deadly combination," said Robert M. Radway, assistant professor of electrical and systems engineering at the University of Pennsylvania. "We attacked it head-on by tightly integrating memory and logic and then building upward at extremely high density. It's like the Manhattan of computing — we can fit more people in less space."
The team worked with SkyWater Technology to fabricate the prototype, grounding the research in real manufacturing constraints rather than pure simulation. That matters: it suggests this isn't a theoretical win but something actually buildable at scale. The result could reshape not just AI hardware but the broader semiconductor industry — a shift toward stacking upward rather than squeezing components ever closer on a flat plane.
The next step is scaling the design, adding more layers, and testing performance on a wider range of workloads beyond AI. If the trajectory holds, you might see these chips powering the next generation of AI systems within the next few years.
