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New Chip Design Trick Saves Engineers Weeks, Billions, and Headaches

Keysight and WIN Semiconductors just launched a workflow to help GaN MMIC developers nail chip fabrication on the first try. This slashes expensive redesigns and delays, accelerating 5G infrastructure.

Elena Voss
Elena Voss
·2 min read·3 views

Originally reported by Interesting Engineering · Rewritten for clarity and brevity by Brightcast

Imagine spending weeks, maybe even months, perfecting a tiny, intricate chip design, sending it off to the factory with a hopeful sigh, only to have it come back… broken. Not just a little bit broken, but fundamentally flawed, requiring a complete do-over. That's the kind of nightmare scenario that has historically plagued engineers in the high-stakes world of chip manufacturing.

But now, two tech giants, Keysight Technologies and WIN Semiconductors, have teamed up to offer a much-needed lifeline. They've cooked up a new design process specifically for gallium nitride (GaN) chips that aims to get it right the first time, every time. Think of it as a chip-designing crystal ball, letting engineers spot problems before the silicon (or in this case, gallium nitride) even sees a factory floor.

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The Digital Time-Saver

This isn't just a minor tweak; it's a full-on workflow overhaul. Instead of a piecemeal approach, the new system integrates everything: on-chip simulations, 3D layout checks, and even designing the evaluation board. This is crucial for companies churning out GaN chips, which are the unsung heroes powering everything from 5G networks and Wi-Fi to satellites and those defense radars you hope never have to be used. A single design failure can delay a project by weeks, racking up costs and causing more than a few gray hairs.

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The secret sauce is connecting Keysight’s design software with WIN Semiconductors’ latest NP 120P GaN Process Design Kit (PDK). This digital handshake allows engineers to perform comprehensive checks and optimizations automatically, catching errors far earlier in the process. It's like having a hyper-vigilant editor for your chip blueprints, but one that also understands quantum physics.

Even after a chip is perfectly fabricated, there’s another hurdle: proving it actually works as expected on an evaluation board. This new workflow tackles that too, letting engineers design and optimize the chip, its package, the circuit board, and all the test connectors simultaneously. It offers a real-world performance preview before anyone even touches the physical hardware.

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The demand for GaN radio-frequency devices is skyrocketing, with experts predicting the global market could hit a cool $2.77 billion by 2031. That kind of growth puts immense pressure on developers to design faster and, more importantly, flawlessly. This new collaboration promises to do just that, streamlining the entire process and getting those advanced RF products to market at warp speed. Which, if you think about it, is both impressive and slightly terrifying.

Brightcast Impact Score (BIS)

This article describes a new design workflow that helps engineers create GaN chips more efficiently, reducing errors and costs. This innovation directly addresses a significant industry problem, offering a scalable solution with clear benefits for various high-tech sectors. The evidence is based on the companies' claims and the inherent value of avoiding costly redesigns.

Hope27/40

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Reach24/30

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Significant
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Sources: Interesting Engineering

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